Integrated Header Switch with Low-Leakage PMOS and High-Leakage NMOS Transistors

ABSTRACT

System and method for providing power with a large on-current and small off-current to circuitry in an integrated circuit. A preferred embodiment comprises a switch for providing power to circuits in an integrated circuit made from a PMOS transistor and an NMOS transistor coupled in parallel. Each transistor&#39;s gate terminal is coupled to a separate control signal line. The PMOS transistor provides current to the circuits at high voltage supply levels while the NMOS transistor provides current to the circuits at low voltage supply levels, wherein the size of the PMOS and NMOS transistor can be changed during design to meet power requirements. Depending upon power requirements, multiple PMOS and NMOS transistors may be used. The combination of PMOS and NMOS transistors permit the use of limited fabrication processes wherein transistor widths can be limited.

This is a division of application Ser. No. 10/916,135, filed on Aug. 11,2004. Benefit of the prior application is claimed.

TECHNICAL FIELD

The present invention relates generally to a system and method forproviding power to integrated circuits, and more particularly to asystem and method for providing power with a large on-current and asmall off-current to circuitry in integrated circuits.

BACKGROUND

In order for logic circuitry in an integrated circuit to operate, it isnecessary to provide power to the logic circuits. To power logiccircuits, it may be necessary to provide a power supply connection and aground connection. Furthermore, in order to minimize power consumptionwhen the logic circuitry is inactive, it is desired that leakage currentbe minimized. Therefore, it is desired to have a large on-current tooff-current ratio.

Header and footer configurations are commonly used ways to provide theconnections to the logic circuits, wherein a header configuration uses aswitch to couple (and decouple) the logic circuits to a power supply anda footer configuration uses a switch to couple (and decouple) the logiccircuits to a ground connection. Therefore, to provide power to thelogic circuits, switches in both the header and the footerconfigurations could close, providing a current path from the powersupply to the ground. For example, in a header configuration, typicallyPMOS (P-type Metal Oxide Semiconductor) transistors can be used as aswitch to cut the power supply connection to the logic circuits, whilein a footer configuration, typically NMOS (N-type Metal OxideSemiconductor) transistors can be used to cut the ground connection tothe logic circuits.

Variations in the header and footer configurations have included the useof high threshold voltage and low threshold voltage PMOS and NMOStransistors to help improve the on-current to off-current ratio. In somevariations, even NMOS transistors have been used as switches in headerconfigurations. In certain manufacturing processes, wherein it may bepossible to create transistors with wide variations in geometries (andother parameters), the use of the header and footer configurations canprovide both a large on-current and small off-current.

One disadvantage of the prior art is that in many manufacturingprocesses wherein the ability to vary the widths of transistors islimited, it may be difficult to use standard transistors in the headerand footer configurations and still provide both a large on-current anda small off-current.

One disadvantage of the prior art is that in many manufacturingprocesses wherein the ability to vary the widths of transistors islimited, it may be difficult to use standard transistors in the headerand footer configurations and still provide both a large on-current anda small off-current.

A second disadvantage of the prior art is that the use of high and lowthreshold voltage transistors may preclude the use of a manufacturingprocess wherein a limited number of transistor sizes may be used. Theuse of transistors with limited sizes can reduce the ability to providea satisfactory on-current to off-current ratio.

SUMMARY OF THE INVENTION

These and other problems are generally solved or circumvented, andtechnical advantages are generally achieved, by preferred embodiments ofthe present invention which provides for a system and method forproviding power with a large on-current and a small off-current tocircuitry in integrated circuits.

In accordance with a preferred embodiment of the present invention, acombination header switch for use in providing power to circuitry in anintegrated circuit, wherein the combination header switch comprises aPMOS (P-type Metal Oxide Semiconductor) transistor having a gateterminal coupled to a first control signal line, an NMOS (N-type MetalOxide Semiconductor) transistor having a gate terminal coupled to asecond control signal line, and wherein each transistor's firstterminals are coupled to a voltage supply and each transistor's secondterminals are coupled to an output of the combination header switch, andwherein the size of the PMOS and NMOS transistors are adjusted toprovide required current levels to the circuitry as a function ofvoltage supply level is provided.

In accordance with another preferred embodiment of the presentinvention, an integrated circuit comprising a logic circuit and acombination header switch coupled between a voltage supply and the logiccircuit, the combination header switch configured to provide current tothe logic circuit as a function of the level of the voltage supply,wherein the combination header switch comprises a PMOS (P-type MetalOxide Semiconductor) transistor having a gate terminal coupled to afirst control signal line, an NMOS (N-type Metal Oxide Semiconductor)transistor having a gate terminal coupled to a second control signalline, and wherein the NMOS transistor comprises a plurality of NMOStransistors coupled in parallel and the PMOS transistor comprises aplurality of PMOS transistors coupled in parallel is provided.

In accordance with yet another preferred embodiment of the presentinvention, a method for designing an integrated circuit, the methodcomprising specifying frequency targets for the logic gates within theintegrated circuit, determining currents to the logic gates based on thefrequency targets, and then sizing a combination header switch so thatthe combination header switch can provide the determined currents isprovided.

An advantage of a preferred embodiment of the present invention is thata header switch with a large on-current to off-current ratio can becreated using a manufacturing process wherein the manufacturing processis not capable of fabricating transistors with a wide range of sizes(and perhaps other parameters). This can enable the use of these limitedfabrication processes, possibly resulting in a lower unit cost for theintegrated circuits since a design with fewer transistor types can beused.

A further advantage of a preferred embodiment of the present inventionis that the design of the header switch can be readily adapted to meetdifferent current needs of different integrated circuits. Therefore, theheader switch can be modified for each integrated circuit design'sneeds, thereby offering optimized performance. Additionally, since theheader switch can be modified for an integrated circuit's needs, thereis no need to used a header switch with more capability than required.This can minimize cost by reducing unneeded hardware.

The foregoing has outlined rather broadly the features and technicaladvantages of the present invention in order that the detaileddescription of the invention that follows may be better understood.Additional features and advantages of the invention will be describedhereinafter which form the subject of the claims of the invention. Itshould be appreciated by those skilled in the art that the conceptionand specific embodiments disclosed may be readily utilized as a basisfor modifying or designing other structures or processes for carryingout the same purposes of the present invention. It should also berealized by those skilled in the art that such equivalent constructionsdo not depart from the spirit and scope of the invention as set forth inthe appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, and theadvantages thereof, reference is now made to the following descriptiontaken in conjunction with the accompanying drawings, in which:

FIG. 1 is a diagram of a schematic of a header configuration used toprovide a voltage supply to a circuit;

FIG. 2 is a digram of a schematic of a footer configuration used toprovide an electrical ground to a circuit;

FIGS. 3 a through 3 c are diagrams of schematics of prior artimplementations of header and footer configurations used to providepower to a circuit while maintaining a high on-current to off-currentratio;

FIG. 4 is a diagram of a high-level view of a schematic of a headerconfiguration used to provide a voltage supply to a logic circuit,wherein a combination switch is used to provide a high on-current tooff-current ratio, according to a preferred embodiment of the presentinvention;

FIG. 5 is a diagram of a schematic of the combination switch, accordingto a preferred embodiment of the present invention;

FIG. 6 a and 6 b are diagrams of schematics of PMOS and NMOS transistorsused in the combination switch, according to a preferred embodiment ofthe present invention;

FIG. 7 is a data plot of exemplary frequency targets as a function ofpower supply voltage, according to a preferred embodiment of the presentinvention;

FIG. 8 is a data plot of current requirements corresponding to theexemplary frequency targets shown in FIG. 7, according to a preferredembodiment of the present invention;

FIG. 9 is a flow diagram of a process for designing a combination switchto meet specified performance requirements, according to a preferredembodiment of the present invention; and

FIG. 10 is a diagram of a layout for an exemplary combination switch,according to a preferred embodiment of the present invention.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the presently preferred embodiments arediscussed in detail below. It should be appreciated, however, that thepresent invention provides many applicable inventive concepts that canbe embodied in a wide variety of specific contexts. The specificembodiments discussed are merely illustrative of specific ways to makeand use the invention, and do not limit the scope of the invention.

The present invention will be described with respect to preferredembodiments in a specific context, namely a header switch for providingpower to logic circuitry in an integrated circuit made using amanufacturing process wherein the process may limit the types oftransistors available. The invention may also be applied, however, toheader switches for use in integrated circuits manufactured using any ofa wide variety of manufacturing processes, from processes with a limitednumber of transistors types to those with unlimited number of transistortypes, where there is interest in minimizing hardware usage and costs.

With reference now to FIG. 1, there is shown a diagram illustrating aschematic of a header configuration 100 used to provide a voltage supplyto a circuit. The header configuration 100 can be used to control theconnection of a voltage supply (“VDD” in this case) to a logic circuit105. Typically, a PMOS (P-type Metal Oxide Semiconductor) transistor 110can be used as a switch to couple (or decouple) the voltage supply tothe logic circuit 105. Depending upon the value of a control signal, thePMOS transistor 110 can be open or closed. When open, the PMOStransistor 110 effectively decouples the logic circuit 105 from thevoltage supply. However, when the PMOS transistor 110 is closed, thelogic circuit 105 is coupled to the voltage supply.

With reference now to FIG. 2, there is shown a diagram illustrating aschematic of a footer configuration 200 used to provide and electricalground to a circuit. The footer configuration 200 can be used to controlthe connection of an electrical ground to a logic circuit 205. Normally,an NMOS (N-type Metal Oxide Semiconductor) transistor 210 can be used asa switch to couple (or decouple) the electrical ground to the logiccircuit 205. Depending upon the value of a control signal, the NMOStransistor 210 can be open or closed. When open, the NMOS transistor 210effectively decouples the logic circuit 205 from the electrical ground.However, when the NMOS transistor 210 is closed, the logic circuit 205is coupled to the electrical ground.

A significant problem with using the header and/or footer configurationfor providing power to logic circuits in an integrated circuit is thatthe transistors used as switches (usually PMOS in a header configurationand NMOS in a footer configuration) can have measurable leakage current,even when they are off. This can be especially true in manufacturingprocesses with limited transistor type availability, wherein thetransistors used as switches are normally the same type as the ones usedin the logic circuits and high threshold voltage transistors aretypically not available for use. The leakage current can result in acurrent drain, even when the logic circuits are supposed to be in an off(or suspended) state. The current drain can increase power consumptionand can result in shorter battery life in wireless applications.

With reference now to FIGS. 3 a through 3 c, there are shown diagramsillustrating schematics of prior art implementations of header andfooter configurations used to provide power to a circuit whilemaintaining a high on-current to off-current ratio. In a limitedmanufacturing process, there are typically no high threshold voltagetransistors available for use in creating a header or footerconfiguration with a high on-current to off-current ratio. Usually, thetransistors available may include core transistors (transistors used inthe fabrication of logic gates) and I/O transistors (transistors used todrive input/output pins). The I/O transistors may have the same geometry(source/drain profiles) as the core transistors but tend to be larger insize. This may imply an abrupt junction with a significant diode leakagecurrent.

FIG. 3 a illustrates a schematic of a prior art header configuration 300using a PMOS core transistor 310 to provide a voltage supply to a logiccircuit 305. This solution is generally unacceptable due to off-statesub-threshold leakage. The effective leakage current reduction may notbe able to exceed a factor of ten (10) due to the need for a large PMOStransistor to deliver sufficient active mode current.

FIG. 3 b illustrates a schematic of a prior art header configuration 320using a PMOS I/O transistor 325 to provide a voltage supply to the logiccircuit 305. The use of the PMOS I/O transistor 325 can provide thenecessary ratio of on-current to off-current, but may be deficient inthat a limit may be place upon the amount of power supply reduction thatcan be achieved when operating in active mode. Not being able to providea full range of low-voltage supplies to the logic circuit 305 can be asignificant disadvantage.

FIG. 3 c illustrates a schematic of a prior art footer configuration 340using an NMOS I/O transistor 345 to provide an electrical ground to thelogic circuit 305. The footer configuration 340 may have a significantadvantage in that the gate of the NMOS I/O transistor 345 can be placedat a voltage potential that is greater than the core voltage. Therefore,a full range of low-voltage supplies can be provided to the logiccircuit 305. However, the NMOS I/O transistor 345 may have an off-stateleakage current that is dominated by the diode leakage typical of coreNMOS transistors, which can be prohibitively large.

With reference now to FIG. 4, there is shown a diagram illustrating ahigh-level view of a schematic of a header configuration 400 used toprovide a voltage supply to a logic circuit 405, wherein a combinationswitch 410 is used to provide a high on-current to off-current ratio,according to a preferred embodiment of the present invention. Theconfiguration of the header configuration 400 is similar to the headerconfiguration 100 (FIG. 1) with a combination switch 410 being used tocontrol a connection between a voltage supply (‘VDD’) and the logiccircuit 405. According to a preferred embodiment of the presentinvention, the combination switch 410 can be made out of a combinationof both PMOS and NMOS transistors, wherein the PMOS transistor can beused to provide the requisite high on-current to off-current ratio andthe NMOS transistor can provide the desired low-voltage operation.Preferably, the PMOS transistor can be fabricated out of an I/Otransistor while the NMOS transistor can be fabricated out of a coretransistor. Note that it may be possible for the combination switch 410to be disjoint with the logic 405. For example, the combination switch410 and the logic 405 may be on different silicon dice, such as on amulti-chip module. Alternatively, the combination switch 410 may beimplemented external to a packaged version of the logic 405.

The combination of the I/O PMOS transistor with the core NMOS transistorin the combination switch 410 can enable low voltage operation withoutcompromising the off-current. According to a preferred embodiment of thepresent invention, the majority of the current provided by thecombination switch 410 is provided by the I/O PMOS transistor whenoperating at high voltage. However, at low operating voltages, the I/OPMOS transistor can be turned off and the core NMOS transistor can beturned on. Since the current requirements at the lower operatingvoltages can be significantly smaller than the current requirements atthe higher operating voltages, a relaxation in the size of the core NMOStransistors can be realized. Note that since the off-current of the coreNMOS transistor can be greater than 100 times the off-current of the I/OPMOS transistor under equivalent biasing conditions, the ability to sizethe core NMOS transistor to be a very small percentage of the size ofthe I/O PMOS transistor can have a positive effect on the off-current. Adetailed description of the determination of the size of the core NMOSand I/O PMOS transistors is presented below.

As discussed above, depending upon the requisite high on-current tooff-current ratio and the desired low-voltage operation, a ratio of PMOSto NMOS transistors can be specified. A key to the design of thecombination switch 410 may be the specification of the size of the PMOSand NMOS transistors so that sufficient high-frequency/high-voltageperformance is provided along with sufficient low-frequency/low-voltageperformance. Note that it may be necessary to use multiple transistorsto meet the overall transistor size requirement. For example, an actualimplementation of the combination switch 410 may use approximately 50PMOS I/O transistors and 5 NMOS core transistors.

The combination switch 410 can be controlled by a pair of controlsignals, “CONTROL_P” and “CONTROL_N.” The control signal “CONTROL_P” canbe used to control the state of the PMOS transistors, while the controlsignal “CONTROL_N” can be used to control the state of the NMOStransistors. Alternatively, a single control signal “CONTROL” can beused to control the state of both the PMOS and the NMOS transistors,wherein the control signal “CONTROL” may be internally inverted whenprovided to either the PMOS or the NMOS transistor.

With reference now to FIG. 5, there is shown a diagram illustrating aschematic of the combination switch 410, according to a preferredembodiment of the present invention. As discussed previously, thecombination switch 410 can be made from a combination of PMOS and NMOStransistors, preferably, an I/O transistor for the PMOS transistor and acore transistor for the NMOS transistor, wherein the size (andtherefore, the number) of the transistors can be adjusted to meetdesired performances specifications. Note that the schematic of thecombination switch 410 shown in FIG. 5 does not convey size and/ornumber information regarding the PMOS and NMOS transistors.

The combination switch 410 comprises a PMOS transistor 505 coupled inparallel with an NMOS transistor 510, with the source terminal of thePMOS transistor 505 and the drain terminal of the NMOS transistor 510being coupled to the voltage supply (“VDD”). The drain terminal of thePMOS transistor 505 and the source terminal of the NMOS transistor 510are coupled together (shown in FIG. 5 as “VDDLSW”) and can be coupled toa logic circuit, such as the logic circuit 405 (FIG. 4). The drainterminal of the PMOS transistor 505 and the sources terminal of the NMOStransistor 510 may be considered to be the output of the combinationswitch 410. A control signal for the PMOS transistor 505, “CONTROL_P,”may be coupled to the gate terminal of the PMOS transistor 505, while acontrol signal for the NMOS transistor 510, “CONTROL_N,” may be coupledto the NMOS transistor's gate terminal. The PMOS transistor 505 and NMOStransistor 510 may have their bulk connections coupled to differentvoltage supplies, “VDD” and “VSS,” respectively. Note that in general,the source and drain terminals of MOS transistors are symmetrical (i.e.,they can be interchangeable), therefore, for discussion purposes, thesource terminal is usually connected to the power supply. However, itcan be possible to change the notation of the terminals of the MOStransistors without changing the spirit of the present invention. As analternative to the combination switch 410 being built out of a PMOStransistor in parallel with an NMOS transistor, where the thresholdvoltage of the PMOS transistor (VTp) is larger (within normalfabrication tolerances) than the threshold of the NMOS transistor (VTn),it may be possible to use a high threshold voltage PMOS transistor inparallel with a low threshold voltage PMOS transistor to create acombination switch (note that this particular configuration is notshown).

As discussed previously, it may be necessary to adjust the size of thePMOS and NMOS transistors used in the combination switch 410 in order tomeet performance requirements. In certain manufacturing processes, itcan be relatively simple to fabricate transistors with differentdimensions. However, in a limited manufacturing process, it may bedifficult (if not impossible) to create transistors with geometriesdifferent from the few allowed in the manufacturing process. One waythat can be used to fabricate large transistors may be to use multipletransistors in place of a single large transistor.

With reference now to FIGS. 6 a and 6 b, there are shown diagramsillustrating schematics of the PMOS and NMOS transistors used in thecombination switch 410, according to a preferred embodiment of thepresent invention. FIG. 6 a displays a possible arrangement forincreasing the size of PMOS transistors, such as the PMOS transistor 505(FIG. 5), when the manufacturing process is limited in creatingtransistors with sizes that differ from the specified sizes. Accordingto a preferred embodiment of the present invention, a plurality of PMOStransistors, such as PMOS transistors 605 and 606, can be arranged inparallel to produce a PMOS transistor with a larger effective size. FIG.6 b displays a similar arrangement for increasing the size of NMOStransistors using a plurality of NMOS transistors, such as NMOStransistors 610 and 611.

As discussed previously, the sizing of the PMOS and NMOS transistors 505and 510 can be adjusted to meet performance requirements. For example,the size of the PMOS transistor 505 can be adjusted to cover thehigh-frequency/high-voltage operation requirements and the size of theNMOS transistor 510 can be adjusted to cover thelow-frequency/low-voltage operation requirements. This can be achievedby specifying operating frequency targets as a function of power supplyvoltage.

With a reference now to FIG. 7, there is shown a data plot illustratingexemplary frequency targets as a function of power supply voltages,according to a preferred embodiment of the present invention. The dataplot displays a series of bars, such as bars 705 and 706, that may berepresentative of logic circuit capability as a function of voltage. Forexample, bar 705 shows that the logic circuit is capable of operating at60% of maximum operating frequency at a voltage supply of 0.95 voltswhile bar 706 shows that the logic circuit is capable of operating at100% of maximum operating frequency at a voltage supply of 1.15 volts.The bars can indicate what is referred to as specified performance,i.e., when a voltage supply at a certain voltage is provided to thelogic circuit, it is expected to operate at a certain percentage ofmaximum operating frequency. Note that the bars (representing operatingfrequency as a function of voltage supply levels) can be different fordifferent circuits and the data plot shown in FIG. 7 may berepresentative of the performance of an exemplary integrated circuit.The data displayed in FIG. 7 should not be construed as being limitingupon the spirit of the present invention.

With the frequency targets specified (displayed in FIG. 7 as bars, suchas the bars 705 and 706), it is now possible to determine an entitledspeed as a function of voltage for the logic circuit. This is displayedin FIG. 7 as the diagonal line 710. The entitled speed provides an upperlimit on the operating frequency of the logic circuit at differentvoltage supply values. Note that it should not be necessary to providepower sufficient for a frequency that the underlying circuit is notcapable of achieving. For example, in FIG. 7, with the voltage supply at0.9 volts, the logic circuit is capable of operating at up to 20% ofmaximum operating frequency. Therefore, even if more power is provided,the logic circuit will not exceed 20% of maximum operating frequency.Ideally, the diagonal line 710 representing the entitled speed should bea simple curve that is monotonic in nature. This can enable easiermatching in subsequent steps.

With reference now to FIG. 8, there is shown a data plot illustratingcurrent requirements corresponding to the exemplary frequency targets asshown in FIG. 7, according to a preferred embodiment of the presentinvention. After determining the speed bins (specifying the frequencytargets as a function of power supply voltage), it may now be possibleto determine the amount of current for each point displayed in the dataplot shown in FIG. 7. The current corresponding to a point in the dataplot can be calculated using the formula: P=V*F (wherein P=power,V=voltage, and F=frequency). In FIG. 8, a first curve 805 displays thenormalized current. The data points for the first curve 805 may beobtained from the frequency targets specified in FIG. 7 multiplied withthe voltage supply voltage.

Based upon the information contained in the first curve 805, the PMOStransistor 505 can be sized to provide the needed current at highervoltage supply levels. A second curve 810 can illustrate the currentprovided by the PMOS transistor 505 as a function of voltage supplylevels. Note however, that at lower voltage supply levels, the currentprovided by the PMOS transistor 505 is not sufficient. Therefore, theNMOS transistor 510 also needs to be sized in order to providesufficient current at lower voltage supply levels. A third curve 815 canillustrate the current provided by the NMOS transistor 510 as a functionof voltage supply levels. Note that at the lower voltage supply levels,the current provided by the NMOS transistor 510 is small, therefore, arelatively small NMOS transistor 510 may be able to provide the neededcurrent. It can be important to minimize the size of the NMOS transistor510 since the off-current of a NMOS transistor can be significantlygreater than the off-current of a PMOS transistor. Therefore, the sizeof the NMOS transistor 510 should be as small as possible and yet stillbe capable of providing the needed current.

The total current provided to the logic circuits can then be defined asa sum of the currents provided by the PMOS transistor 505 and the NMOStransistor 510. A fourth curve 820 illustrates the total currentprovided to the logic circuits and is the sum of the second curve 810and the third curve 815. Note that at all voltage supply levels, thefourth curve 820 (the current provided by the combination switch 410) isgreater than or equal to the first curve 805 (the current needed by thelogic circuits at different voltage supply levels).

When the current to be provided to the circuitry in the integratedcircuit can be specified as a function of voltage supply level, it maythen be possible to provide just enough current to the circuitry insteadof providing more current than necessary. For example, as shown in FIG.8 (the first curve 805 and the fourth curve 820) the current required bythe circuitry at a low voltage supply level may be only a small fractionof the current required by the circuitry at a high voltage supply level(less than 50 mA at 0.7 volts as compared to approximately 1 A at 1.3volts). Therefore, a simple power supply may be designed to provide 1 Aat all voltage levels, while an optimized power supply could be designedto provide slightly more current than needed at different voltagelevels. The simple power supply may then have difficulty providing 1 Aat 0.7 volts and still have a high on-current to off-current ratio.

With reference now to FIG. 9, there is shown a flow diagram illustratinga process 900 for designing the combination switch 410 to meet specifiedperformance requirements, according to a preferred embodiment of thepresent invention. The process 900 may illustrate the design of thecombination switch 410 to meet a particular set of performancerequirements. The process 900 may begin with a designer of thecombination switch 410 defining a set of frequency targets for logiccircuits that will make use of the combination switch 410 (block 905).As discussed previously, the frequency targets can be specified for arange of different voltage supply levels. Note that the frequency targetpoints may have been specified for the designer. From the set offrequency targets, the designer can determine a corresponding set ofcurrent requirements (block 910). The set of current requirements can beused as a design specification for the combination switch 410, whereinthe combination switch 410 must meet or exceed the set of currentrequirements.

Using set of current requirements (determined in block 910), thedesigner can size the PMOS transistors (block 915) to provide the neededcurrent at the higher ranges of the voltage supply levels and the NMOStransistors (block 920) to provide the needed current at the lowerranges of the voltage supply levels. The designer can make use ofdifferent computer aided engineering or design tools available todetermine the proper sizing for the PMOS and NMOS transistors. Thedesigner can then verify (through the use of engineering and/orsimulation tools) that the combination switch 410 with the properlysized PMOS and NMOS transistors can meet the current requirements of thelogic circuits in the range of voltage supply levels (block 925). If thecombinations switch 410 does indeed meet the current requirements, thenthe design process is complete and can terminate. If the combinationswitch 410 does not meet the current requirements, then the designer mayneed to return to blocks 915 and 920 to redesign the combination switch410. The process 900 can continue until a design for the combinationswitch 410 meeting the current requirements is made.

With reference now to FIG. 10, there is shown a diagram illustrating alayout 1000 of an exemplary combination switch, according to a preferredembodiment of the present invention. The layout 1000 of the combinationswitch meets a set of performance specifications, such as the currentrequirements shown in FIG. 8. The layout 1000 shows a combination switchmade from two banks of PMOS transistors 1005 and 10101 and a bank ofNMOS transistors 1015, the NMOS transistors located between the twobanks of PMOS transistors. Note that due to fabrication processrestrictions on the size of transistors, the PMOS and NMOS transistorsused in the combination switch is made from a plurality of transistorscoupled together in parallel. Logically, the two banks of PMOStransistors 1005 and 1010 can be represented as a single PMOStransistor, such as the PMOS transistor 505 (FIG. 5) and the bank ofNMOS transistors 1015 can be represented as a single NMOS transistor,such as the NMOS transistor 510 (FIG. 5).

Although the present invention and its advantages have been described indetail, it should be understood that various changes, substitutions andalterations can be made herein without departing from the spirit andscope of the invention as defined by the appended claims.

Moreover, the scope of the present application is not intended to belimited to the particular embodiments of the process, machine,manufacture, composition of matter, means, methods and steps describedin the specification. As one of ordinary skill in the art will readilyappreciate from the disclosure of the present invention, processes,machines, manufacture, compositions of matter, means, methods, or steps,presently existing or later to be developed, that perform substantiallythe same function or achieve substantially the same result as thecorresponding embodiments described herein may be utilized according tothe present invention. Accordingly, the appended claims are intended toinclude within their scope such processes, machines, manufacture,compositions of matter, means, methods, or steps.

1-14. (canceled)
 15. A method for designing an integrated circuit, themethod comprising: specifying frequency targets for operation of logicgates within the integrated circuit; determining currents to flow to thelogic gates, the determining being based on the frequency targets; andsizing a combination header switch that will be coupled between thelogic gates and a voltage supply so that the combination header switchcan provide the determined currents.
 16. The method of claim 15, whereinthe combination header switch comprises a plurality of PMOS transistorscoupled in parallel with a plurality of NMOS transistors, and whereinsizing the combination header switch determines the number oftransistors in the plurality of PMOS transistors and the number oftransistors in the plurality of NMOS transistors.
 17. The method ofclaim 16, wherein the frequency targets are specified for a range ofvoltage supply levels.
 18. The method of claim 17, wherein there are aplurality of frequency targets, and wherein the currents are determinedby multiplying each frequency target with an associated voltage supplylevel.
 19. The method of claim 16, wherein the frequency targets arespecified for a range of voltage supply levels, and wherein the sizingcomprises: selecting the number of PMOS transistors to provide currentat high voltage supply levels; and selecting the number of NMOStransistors to provide current at low voltage supply levels.
 20. Themethod of claim 16 further comprising after the sizing, verifying thatthe combination header switch can provide the determined currents. 21.The method of claim 20, wherein the sizing and verifying is repeateduntil the combination header switch can provide the determined currents.22. The method of claim 15, wherein the frequency targets are specifiedfor a range of voltage supply levels, and wherein the sizing comprises:determining a width and a length of the PMOS transistor to providecurrent at high voltage supply levels; and determining a width and alength of the NMOS transistor to provide current at low voltage supplylevels.